Referring to FIG. 1, a conventional III-nitride power semiconductor device includes a III-nitride heterojunction body 10. III-nitride heterojunction body 10 includes first III-nitride semiconductor body 12 formed with one III-nitride semiconductor alloy (e.g. GaN) and second III-nitride semiconductor body 14 on body 12 formed with another III-nitride semiconductor alloy having a band gap different from that of first III-nitride semiconductor body 12 (e.g. AlGaN).
As is known, the composition and thickness of each III-nitride semiconductor body 12, 14 is selected to generate a two-dimensional electron gas 16 (2-DEG) at the heterojunction of the two bodies 12, 14.
2-DEG 16 to generated is rich in carriers and serves as a conductive channel between a first power electrode 18 (e.g. source electrode) which is ohmically coupled to second III-nitride body 14 and second power electrode 20 (e.g. drain electrode) which is also ohmically coupled to second III-nitride body 14. To control the state of conductivity between first power electrode 18 and second power electrode 20, a gate arrangement 22 is disposed between first 18 and second 20 power electrodes, which may reside on second III-nitride body 14. Gate arrangement 22, for example, may include a schottky body in schottky contact with second III-nitride body 14, or alternatively may include a gate insulation body and a gate electrode capacitively coupled to 2-DEG 16 through the gate insulation.
III-nitride heterojunction 10, in a conventional design, is disposed over a substrate 28. Typically, a transition body 30 is disposed between substrate 28 and heterojunction 10. A passivation body 32 through which electrodes 18, 20 are in contact with body 14 may be also provided to protect the active portion of heterojunction 10.
It has been observed that high electric field build-up near the gate arrangement results in gate breakdown (particularly at the edge closest to the drain electrode of the device). Other disadvantages include low drain-source breakdown voltage, and time dependent degradation of device parameters due to hot carriers and charge trapping. FIG. 3 illustrates schematically electric field lines 24 near the edges of gate arrangement 22 of a device according to FIG. 1.
Referring to FIG. 2, to improve the capability of a III-nitride device to withstand breakdown at the edges of its gate, a field plate 26 is provided that extends laterally from, for example, the gate electrode of the device over passivation body 32 toward a power electrode (e.g. drain electrode) of the device. The provision of field plate 26 reduces the strength of the electric field at the edge of gate arrangement 22 by spreading the field lines 27 as illustrated schematically in FIG. 4.
While field plate 26 can reduce the intensity of the electric field and improve the breakdown voltage of the device it is disadvantageous because:
1. it increases the active area of the device;
2. while it causes the movement of the point of high electric field to the edge of field plate 25, it may still allow changes to occur;
3. the increase gate-drain overlap capacitance degrades high frequency switching and increases switching losses, which is worsened by the Miller Effect.